张涛,邹百威.一种低延时低功耗PWM比较器电路设计[J]. 微电子学与计算机,2024,41(3):112-117. doi: 10.19304/J.ISSN1000-7180.2023.0109
引用本文: 张涛,邹百威.一种低延时低功耗PWM比较器电路设计[J]. 微电子学与计算机,2024,41(3):112-117. doi: 10.19304/J.ISSN1000-7180.2023.0109
ZHANG T,ZOU B W. A low delay low power PWM comparator circuit design[J]. Microelectronics & Computer,2024,41(3):112-117. doi: 10.19304/J.ISSN1000-7180.2023.0109
Citation: ZHANG T,ZOU B W. A low delay low power PWM comparator circuit design[J]. Microelectronics & Computer,2024,41(3):112-117. doi: 10.19304/J.ISSN1000-7180.2023.0109

一种低延时低功耗PWM比较器电路设计

A low delay low power PWM comparator circuit design

  • 摘要: 设计了一种基于HHGrace 0.35 μm BCD工艺的低延时低功耗电压型静态脉冲宽度调制(Pulse Width Modulation, PWM)比较器,主要应用于高频低功耗的开关电源系统。设计中包含动态尾电流源和改进型正反馈放大器,以改进传统跨导放大器(Operational Transconductance Amplifier, OTA)型比较器高延迟和高功耗等问题。仿真结果表明:在1.2 ~ 5.0 V供电电压范围内稳定工作,最大上升沿延时35 ns,最大下降沿延时41 ns,支持6 MHz开关频率的系统,比较精度8 mV,失调电压439 μV,静态功耗仅为2.5 μA(1.2 V供电)和4.4 μA(5.0 V供电)。

     

    Abstract: A low delay and low power voltage type static Pulse Width Modulation (PWM) comparator based on HHGrace 0.35 μm BCD process is designed, which is mainly used in high frequency and low power switching power supply systems. The design includes a dynamic tail current source and an improved positive feedback amplifier to improve the high latency and power consumption of traditional Operational Transconductance Amplifier (OTA) comparators. The simulation results show that the system works stably in the supply voltage range of 1.2 - 5.0 V, the maximum rising edge delay is 35 ns, the maximum falling edge delay is 41 ns, the system supports the switching frequency of 6 MHz, the comparison accuracy is 8 mV, the offset voltage is 439 μV, and the static power consumption is only 2.5 μA (1.2 V) and 4.4 μA (5.0 V).

     

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