Subtraction topology reconfigurable multiphase switched capacitor DC-DC converter with conductance modulation

A subtraction topology of the reconfigurable multiphase switched capacitor DC-DC converter is presented to realize the conversion ratios of 1/2 and 2/3. In 2/3 mode, the parasitic loss of the serial-parallel topology is reduced by the subtraction topology. This paper presents the small signal model of the multiphase switched capacitor DC-DC converter loop under PFM control, which provides the optimal selection scheme for the switching frequency and the size of the transistors at a given load condition. The comparator is adopted to realize the adaptive modulation of the conductance of the transistors to further improve the efficiency. The simulation results show that under 2.2 V input voltage in the TSMC-40nm process, the proposed converter achieves 20 MHz bandwidth. The recovery time of the transient response is 40ns. In 1/2 mode, this converter achieves the peak efficiency of 85.2% and the power density of 280 mW/mm2. In 2/3 mode, the peak efficiency is 83.7% and the power density is 320 mW/mm².